The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including at least one vertical transport field effect transistor (FET) having a gradient threshold voltage, and a method of forming such a structure.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor fin (or pillar) defines the channel with the source and drain located at opposing ends of the semiconductor fin. Vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
The lateral asymmetric channel (LAC) doping profile approach provides one of the most effective ways to improve the electrical characteristics of transistor devices. For LAC devices, the doping concentration of the source side is higher than that of the drain side in the channel. The channel potential transition at the source side channel region is much stepper than that of the other channel regions, while the device is operating due to non-uniform channel doping. Such a steep potential distribution near the source side enhances the lateral channel electric field and this increases the carrier mobility. This approach, however, suffers from channel dopant diffusion and dopant variation. Also, it is difficult to design short channel devices using the LAC approach. There is thus a need for providing a vertical transport field effect transistor (FET) having improved electrical characteristics and device performance.